voltage_trimming_GADC

This calibration measures the optimal settings for the VDDA/D trim bits to reach the desired 1.2 V output for each channel on the chip by monitoring voltage registers using the RD53B internal GADC.

Usage: dirigent voltage_trimming_GADC [OPTIONS]

Options:
    -i, --start-setting     Trim bit setting to begin sweep [default: 0]
    -f, --stop-setting      Trim bit setting to end sweep [default: 15]
    -m, --monitors,         A list of monitoring parameters to enable in Ph2 ACF for this scan e.g. ['VIND', 'VDDA'].
    --help                  Show this message and exit.